General

What are some language constructs that should generally be avoided for Verilog/VHDL compatibility?

CDC

How to safely pass a one bit signal between clock domains?

Design a FIFO

Xilinx

What is TIG? When should it be used? (this is a touchy subject which IMHO makes great interview q)

Whats the difference between a DCM and a PLL?

What are some differences between ISE .ucf constraints and Vivado .xdc constraints?

ISE

Constraints

What is KEEP vs S(AVE) constraint?

What are some constraints that you

Which xilinx tools directly use .ucf files?

What are some constraints you can specify in .ucf but not in .v/.vhd?

Place and route passes timing but trce fails timing. What can cause this?

What is LOC vs RLOC constraint? When should they be used?

Show several ways to specify constraints in Verilog and/or VHDL

Whats the difference between a net (NET) and a timing net (TNM_NET)?

Give an example ISE automaticly inferring timing constraints

Name some IP cores that you must add period constraints to. Why do you need to add these?

Why can't a period and a TO/FROM be placed on the same TNM? How do you work around this?

Whats one way that a net can be removed even with a KEEP constraint? How do you prevent this?

Files

Probably only applicable if you use command line flow

What type of files are used in a coregen workflow?

Primitives

Actel

 
interview.txt · Last modified: 2014/07/10 16:04 by mcmaster-guest
 
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