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process_tech [2015/12/17 17:49] azonenberg [Cheesing / bamboo structures] |
process_tech [2015/12/17 17:52] (current) azonenberg [Eight or more layers] |
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| Many dense interconnect layers, as with 4-7 layer devices, but with the addition of a dedicated power layer (or layers) on top metal for improved power distribution performance and to avoid cluttering high-density interconnect layers with power busing. | Many dense interconnect layers, as with 4-7 layer devices, but with the addition of a dedicated power layer (or layers) on top metal for improved power distribution performance and to avoid cluttering high-density interconnect layers with power busing. | ||
| - | Example image (Xilinx XC6SLX4, 45nm Samsung process, probably ~12 layers). Top metal wires are massive, at least 5μm. | + | Example image (Xilinx XC6SLX4, 45nm Samsung process, 9 layers). Top metal wires are massive, at least 5μm. |
| {{:azonenberg:process_examples:topmetal_power.jpg?600|}} | {{:azonenberg:process_examples:topmetal_power.jpg?600|}} | ||